\doxysection{mpu\+\_\+armv7.\+h}
\hypertarget{mpu__armv7_8h_source}{}\label{mpu__armv7_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/mpu\_armv7.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/mpu\_armv7.h}}

\begin{DoxyCode}{0}
\DoxyCodeLine{00001\ \textcolor{comment}{/******************************************************************************}}
\DoxyCodeLine{00002\ \textcolor{comment}{\ *\ @file\ \ \ \ \ mpu\_armv7.h}}
\DoxyCodeLine{00003\ \textcolor{comment}{\ *\ @brief\ \ \ \ CMSIS\ MPU\ API\ for\ Armv7-\/M\ MPU}}
\DoxyCodeLine{00004\ \textcolor{comment}{\ *\ @version\ \ V5.1.0}}
\DoxyCodeLine{00005\ \textcolor{comment}{\ *\ @date\ \ \ \ \ 08.\ March\ 2019}}
\DoxyCodeLine{00006\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{00007\ \textcolor{comment}{/*}}
\DoxyCodeLine{00008\ \textcolor{comment}{\ *\ Copyright\ (c)\ 2017-\/2019\ Arm\ Limited.\ All\ rights\ reserved.}}
\DoxyCodeLine{00009\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00010\ \textcolor{comment}{\ *\ SPDX-\/License-\/Identifier:\ Apache-\/2.0}}
\DoxyCodeLine{00011\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00012\ \textcolor{comment}{\ *\ Licensed\ under\ the\ Apache\ License,\ Version\ 2.0\ (the\ License);\ you\ may}}
\DoxyCodeLine{00013\ \textcolor{comment}{\ *\ not\ use\ this\ file\ except\ in\ compliance\ with\ the\ License.}}
\DoxyCodeLine{00014\ \textcolor{comment}{\ *\ You\ may\ obtain\ a\ copy\ of\ the\ License\ at}}
\DoxyCodeLine{00015\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00016\ \textcolor{comment}{\ *\ www.apache.org/licenses/LICENSE-\/2.0}}
\DoxyCodeLine{00017\ \textcolor{comment}{\ *}}
\DoxyCodeLine{00018\ \textcolor{comment}{\ *\ Unless\ required\ by\ applicable\ law\ or\ agreed\ to\ in\ writing,\ software}}
\DoxyCodeLine{00019\ \textcolor{comment}{\ *\ distributed\ under\ the\ License\ is\ distributed\ on\ an\ AS\ IS\ BASIS,\ WITHOUT}}
\DoxyCodeLine{00020\ \textcolor{comment}{\ *\ WARRANTIES\ OR\ CONDITIONS\ OF\ ANY\ KIND,\ either\ express\ or\ implied.}}
\DoxyCodeLine{00021\ \textcolor{comment}{\ *\ See\ the\ License\ for\ the\ specific\ language\ governing\ permissions\ and}}
\DoxyCodeLine{00022\ \textcolor{comment}{\ *\ limitations\ under\ the\ License.}}
\DoxyCodeLine{00023\ \textcolor{comment}{\ */}}
\DoxyCodeLine{00024\ \ }
\DoxyCodeLine{00025\ \textcolor{preprocessor}{\#if\ \ \ defined\ (\ \_\_ICCARM\_\_\ )}}
\DoxyCodeLine{00026\ \textcolor{preprocessor}{\ \ \#pragma\ system\_include\ \ \ \ \ \ \ \ \ }\textcolor{comment}{/*\ treat\ file\ as\ system\ include\ file\ for\ MISRA\ check\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00027\ \textcolor{preprocessor}{\#elif\ defined\ (\_\_clang\_\_)}}
\DoxyCodeLine{00028\ \textcolor{preprocessor}{\ \ \#pragma\ clang\ system\_header\ \ \ \ }\textcolor{comment}{/*\ treat\ file\ as\ system\ include\ file\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{00029\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00030\ \ }
\DoxyCodeLine{00031\ \textcolor{preprocessor}{\#ifndef\ ARM\_MPU\_ARMV7\_H}}
\DoxyCodeLine{00032\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_ARMV7\_H}}
\DoxyCodeLine{00033\ }
\DoxyCodeLine{00034\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_32B\ \ \ \ \ \ ((uint8\_t)0x04U)\ }}
\DoxyCodeLine{00035\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_64B\ \ \ \ \ \ ((uint8\_t)0x05U)\ }}
\DoxyCodeLine{00036\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_128B\ \ \ \ \ ((uint8\_t)0x06U)\ }}
\DoxyCodeLine{00037\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_256B\ \ \ \ \ ((uint8\_t)0x07U)\ }}
\DoxyCodeLine{00038\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_512B\ \ \ \ \ ((uint8\_t)0x08U)\ }}
\DoxyCodeLine{00039\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_1KB\ \ \ \ \ \ ((uint8\_t)0x09U)\ }}
\DoxyCodeLine{00040\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_2KB\ \ \ \ \ \ ((uint8\_t)0x0AU)\ }}
\DoxyCodeLine{00041\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_4KB\ \ \ \ \ \ ((uint8\_t)0x0BU)\ }}
\DoxyCodeLine{00042\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_8KB\ \ \ \ \ \ ((uint8\_t)0x0CU)\ }}
\DoxyCodeLine{00043\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_16KB\ \ \ \ \ ((uint8\_t)0x0DU)\ }}
\DoxyCodeLine{00044\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_32KB\ \ \ \ \ ((uint8\_t)0x0EU)\ }}
\DoxyCodeLine{00045\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_64KB\ \ \ \ \ ((uint8\_t)0x0FU)\ }}
\DoxyCodeLine{00046\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_128KB\ \ \ \ ((uint8\_t)0x10U)\ }}
\DoxyCodeLine{00047\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_256KB\ \ \ \ ((uint8\_t)0x11U)\ }}
\DoxyCodeLine{00048\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_512KB\ \ \ \ ((uint8\_t)0x12U)\ }}
\DoxyCodeLine{00049\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_1MB\ \ \ \ \ \ ((uint8\_t)0x13U)\ }}
\DoxyCodeLine{00050\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_2MB\ \ \ \ \ \ ((uint8\_t)0x14U)\ }}
\DoxyCodeLine{00051\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_4MB\ \ \ \ \ \ ((uint8\_t)0x15U)\ }}
\DoxyCodeLine{00052\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_8MB\ \ \ \ \ \ ((uint8\_t)0x16U)\ }}
\DoxyCodeLine{00053\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_16MB\ \ \ \ \ ((uint8\_t)0x17U)\ }}
\DoxyCodeLine{00054\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_32MB\ \ \ \ \ ((uint8\_t)0x18U)\ }}
\DoxyCodeLine{00055\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_64MB\ \ \ \ \ ((uint8\_t)0x19U)\ }}
\DoxyCodeLine{00056\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_128MB\ \ \ \ ((uint8\_t)0x1AU)\ }}
\DoxyCodeLine{00057\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_256MB\ \ \ \ ((uint8\_t)0x1BU)\ }}
\DoxyCodeLine{00058\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_512MB\ \ \ \ ((uint8\_t)0x1CU)\ }}
\DoxyCodeLine{00059\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_1GB\ \ \ \ \ \ ((uint8\_t)0x1DU)\ }}
\DoxyCodeLine{00060\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_2GB\ \ \ \ \ \ ((uint8\_t)0x1EU)\ }}
\DoxyCodeLine{00061\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_REGION\_SIZE\_4GB\ \ \ \ \ \ ((uint8\_t)0x1FU)\ }}
\DoxyCodeLine{00062\ }
\DoxyCodeLine{00063\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_AP\_NONE\ 0U\ }}
\DoxyCodeLine{00064\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_AP\_PRIV\ 1U\ }}
\DoxyCodeLine{00065\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_AP\_URO\ \ 2U\ }}
\DoxyCodeLine{00066\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_AP\_FULL\ 3U\ }}
\DoxyCodeLine{00067\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_AP\_PRO\ \ 5U\ }}
\DoxyCodeLine{00068\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_AP\_RO\ \ \ 6U\ }}
\DoxyCodeLine{00069\ }
\DoxyCodeLine{00075\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_RBAR(Region,\ BaseAddress)\ \(\backslash\)}}
\DoxyCodeLine{00076\ \textcolor{preprocessor}{\ \ (((BaseAddress)\ \&\ MPU\_RBAR\_ADDR\_Msk)\ |\ \ \(\backslash\)}}
\DoxyCodeLine{00077\ \textcolor{preprocessor}{\ \ \ ((Region)\ \&\ MPU\_RBAR\_REGION\_Msk)\ \ \ \ |\ \ \(\backslash\)}}
\DoxyCodeLine{00078\ \textcolor{preprocessor}{\ \ \ (MPU\_RBAR\_VALID\_Msk))}}
\DoxyCodeLine{00079\ \ \ }
\DoxyCodeLine{00088\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_ACCESS\_(TypeExtField,\ IsShareable,\ IsCacheable,\ IsBufferable)\ \ \ \(\backslash\)}}
\DoxyCodeLine{00089\ \textcolor{preprocessor}{\ \ ((((TypeExtField)\ <<\ MPU\_RASR\_TEX\_Pos)\ \&\ MPU\_RASR\_TEX\_Msk)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ \(\backslash\)}}
\DoxyCodeLine{00090\ \textcolor{preprocessor}{\ \ \ (((IsShareable)\ \ <<\ MPU\_RASR\_S\_Pos)\ \ \ \&\ MPU\_RASR\_S\_Msk)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ \(\backslash\)}}
\DoxyCodeLine{00091\ \textcolor{preprocessor}{\ \ \ (((IsCacheable)\ \ <<\ MPU\_RASR\_C\_Pos)\ \ \ \&\ MPU\_RASR\_C\_Msk)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ \(\backslash\)}}
\DoxyCodeLine{00092\ \textcolor{preprocessor}{\ \ \ (((IsBufferable)\ <<\ MPU\_RASR\_B\_Pos)\ \ \ \&\ MPU\_RASR\_B\_Msk))}}
\DoxyCodeLine{00093\ }
\DoxyCodeLine{00103\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_RASR\_EX(DisableExec,\ AccessPermission,\ AccessAttributes,\ SubRegionDisable,\ Size)\ \ \ \ \(\backslash\)}}
\DoxyCodeLine{00104\ \textcolor{preprocessor}{\ \ ((((DisableExec)\ \ \ \ \ \ <<\ MPU\_RASR\_XN\_Pos)\ \ \ \&\ MPU\_RASR\_XN\_Msk)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ \(\backslash\)}}
\DoxyCodeLine{00105\ \textcolor{preprocessor}{\ \ \ (((AccessPermission)\ <<\ MPU\_RASR\_AP\_Pos)\ \ \ \&\ MPU\_RASR\_AP\_Msk)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ \(\backslash\)}}
\DoxyCodeLine{00106\ \textcolor{preprocessor}{\ \ \ (((AccessAttributes)\ \&\ (MPU\_RASR\_TEX\_Msk\ |\ MPU\_RASR\_S\_Msk\ |\ MPU\_RASR\_C\_Msk\ |\ MPU\_RASR\_B\_Msk)))\ |\ \(\backslash\)}}
\DoxyCodeLine{00107\ \textcolor{preprocessor}{\ \ \ (((SubRegionDisable)\ <<\ MPU\_RASR\_SRD\_Pos)\ \ \&\ MPU\_RASR\_SRD\_Msk)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ \(\backslash\)}}
\DoxyCodeLine{00108\ \textcolor{preprocessor}{\ \ \ (((Size)\ \ \ \ \ \ \ \ \ \ \ \ \ <<\ MPU\_RASR\_SIZE\_Pos)\ \&\ MPU\_RASR\_SIZE\_Msk)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |\ \(\backslash\)}}
\DoxyCodeLine{00109\ \textcolor{preprocessor}{\ \ \ (((MPU\_RASR\_ENABLE\_Msk))))}}
\DoxyCodeLine{00110\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{00123\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_RASR(DisableExec,\ AccessPermission,\ TypeExtField,\ IsShareable,\ IsCacheable,\ IsBufferable,\ SubRegionDisable,\ Size)\ \(\backslash\)}}
\DoxyCodeLine{00124\ \textcolor{preprocessor}{\ \ ARM\_MPU\_RASR\_EX(DisableExec,\ AccessPermission,\ ARM\_MPU\_ACCESS\_(TypeExtField,\ IsShareable,\ IsCacheable,\ IsBufferable),\ SubRegionDisable,\ Size)}}
\DoxyCodeLine{00125\ \ }
\DoxyCodeLine{00133\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_ACCESS\_ORDERED\ ARM\_MPU\_ACCESS\_(0U,\ 1U,\ 0U,\ 0U)}}
\DoxyCodeLine{00134\ \ }
\DoxyCodeLine{00144\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_ACCESS\_DEVICE(IsShareable)\ ((IsShareable)\ ?\ ARM\_MPU\_ACCESS\_(0U,\ 1U,\ 0U,\ 1U)\ :\ ARM\_MPU\_ACCESS\_(2U,\ 0U,\ 0U,\ 0U))}}
\DoxyCodeLine{00145\ \ }
\DoxyCodeLine{00157\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_ACCESS\_NORMAL(OuterCp,\ InnerCp,\ IsShareable)\ ARM\_MPU\_ACCESS\_((4U\ |\ (OuterCp)),\ IsShareable,\ ((InnerCp)\ \&\ 2U),\ ((InnerCp)\ \&\ 1U))}}
\DoxyCodeLine{00158\ }
\DoxyCodeLine{00162\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_CACHEP\_NOCACHE\ 0U}}
\DoxyCodeLine{00163\ }
\DoxyCodeLine{00167\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_CACHEP\_WB\_WRA\ 1U}}
\DoxyCodeLine{00168\ }
\DoxyCodeLine{00172\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_CACHEP\_WT\_NWA\ 2U}}
\DoxyCodeLine{00173\ }
\DoxyCodeLine{00177\ \textcolor{preprocessor}{\#define\ ARM\_MPU\_CACHEP\_WB\_NWA\ 3U}}
\DoxyCodeLine{00178\ }
\DoxyCodeLine{00179\ }
\DoxyCodeLine{00183\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct\ }\{}
\DoxyCodeLine{00184\ \ \ uint32\_t\ \mbox{\hyperlink{struct_a_r_m___m_p_u___region__t_afe7a7721aa08988d915670efa432cdd2}{RBAR}};\ }
\DoxyCodeLine{00185\ \ \ uint32\_t\ \mbox{\hyperlink{struct_a_r_m___m_p_u___region__t_a38c1d3bc6a9ffc9423d633add01928f1}{RASR}};\ }
\DoxyCodeLine{00186\ \}\ \mbox{\hyperlink{struct_a_r_m___m_p_u___region__t}{ARM\_MPU\_Region\_t}};}
\DoxyCodeLine{00187\ \ \ \ \ }
\DoxyCodeLine{00191\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ ARM\_MPU\_Enable(uint32\_t\ MPU\_Control)}
\DoxyCodeLine{00192\ \{}
\DoxyCodeLine{00193\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>CTRL\ =\ MPU\_Control\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae72b283f6e38b641c877182f03d95844}{MPU\_CTRL\_ENABLE\_Msk}};}
\DoxyCodeLine{00194\ \textcolor{preprocessor}{\#ifdef\ SCB\_SHCSR\_MEMFAULTENA\_Msk}}
\DoxyCodeLine{00195\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHCSR\ |=\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf084424fa1f69bea36a1c44899d83d17}{SCB\_SHCSR\_MEMFAULTENA\_Msk}};}
\DoxyCodeLine{00196\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00197\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{00198\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{00199\ \}}
\DoxyCodeLine{00200\ }
\DoxyCodeLine{00203\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ ARM\_MPU\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{00204\ \{}
\DoxyCodeLine{00205\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga671101179b5943990785f36f8c1e2269}{\_\_DMB}}();}
\DoxyCodeLine{00206\ \textcolor{preprocessor}{\#ifdef\ SCB\_SHCSR\_MEMFAULTENA\_Msk}}
\DoxyCodeLine{00207\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHCSR\ \&=\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaf084424fa1f69bea36a1c44899d83d17}{\string~SCB\_SHCSR\_MEMFAULTENA\_Msk}};}
\DoxyCodeLine{00208\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{00209\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>CTRL\ \ \&=\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gae72b283f6e38b641c877182f03d95844}{\string~MPU\_CTRL\_ENABLE\_Msk}};}
\DoxyCodeLine{00210\ \}}
\DoxyCodeLine{00211\ }
\DoxyCodeLine{00215\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ ARM\_MPU\_ClrRegion(uint32\_t\ rnr)}
\DoxyCodeLine{00216\ \{}
\DoxyCodeLine{00217\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RNR\ =\ rnr;}
\DoxyCodeLine{00218\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RASR\ =\ 0U;}
\DoxyCodeLine{00219\ \}}
\DoxyCodeLine{00220\ \ \ \ }
\DoxyCodeLine{00225\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ ARM\_MPU\_SetRegion(uint32\_t\ rbar,\ uint32\_t\ rasr)}
\DoxyCodeLine{00226\ \{}
\DoxyCodeLine{00227\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RBAR\ =\ rbar;}
\DoxyCodeLine{00228\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RASR\ =\ rasr;}
\DoxyCodeLine{00229\ \}}
\DoxyCodeLine{00230\ \ \ \ }
\DoxyCodeLine{00236\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ ARM\_MPU\_SetRegionEx(uint32\_t\ rnr,\ uint32\_t\ rbar,\ uint32\_t\ rasr)}
\DoxyCodeLine{00237\ \{}
\DoxyCodeLine{00238\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RNR\ =\ rnr;}
\DoxyCodeLine{00239\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RBAR\ =\ rbar;}
\DoxyCodeLine{00240\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RASR\ =\ rasr;}
\DoxyCodeLine{00241\ \}}
\DoxyCodeLine{00242\ }
\DoxyCodeLine{00248\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ ARM\_MPU\_OrderedMemcpy(\textcolor{keyword}{volatile}\ uint32\_t*\ dst,\ \textcolor{keyword}{const}\ uint32\_t*\ \_\_RESTRICT\ src,\ uint32\_t\ len)}
\DoxyCodeLine{00249\ \{}
\DoxyCodeLine{00250\ \ \ uint32\_t\ i;}
\DoxyCodeLine{00251\ \ \ \textcolor{keywordflow}{for}\ (i\ =\ 0U;\ i\ <\ len;\ ++i)\ }
\DoxyCodeLine{00252\ \ \ \{}
\DoxyCodeLine{00253\ \ \ \ \ dst[i]\ =\ src[i];}
\DoxyCodeLine{00254\ \ \ \}}
\DoxyCodeLine{00255\ \}}
\DoxyCodeLine{00256\ }
\DoxyCodeLine{00261\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ ARM\_MPU\_Load(\mbox{\hyperlink{struct_a_r_m___m_p_u___region__t}{ARM\_MPU\_Region\_t}}\ \textcolor{keyword}{const}*\ table,\ uint32\_t\ cnt)\ }
\DoxyCodeLine{00262\ \{}
\DoxyCodeLine{00263\ \ \ \textcolor{keyword}{const}\ uint32\_t\ rowWordSize\ =\ \textcolor{keyword}{sizeof}(\mbox{\hyperlink{struct_a_r_m___m_p_u___region__t}{ARM\_MPU\_Region\_t}})/4U;}
\DoxyCodeLine{00264\ \ \ \textcolor{keywordflow}{while}\ (cnt\ >\ MPU\_TYPE\_RALIASES)\ \{}
\DoxyCodeLine{00265\ \ \ \ \ ARM\_MPU\_OrderedMemcpy(\&(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RBAR),\ \&(table-\/>\mbox{\hyperlink{struct_a_r_m___m_p_u___region__t_afe7a7721aa08988d915670efa432cdd2}{RBAR}}),\ MPU\_TYPE\_RALIASES*rowWordSize);}
\DoxyCodeLine{00266\ \ \ \ \ table\ +=\ MPU\_TYPE\_RALIASES;}
\DoxyCodeLine{00267\ \ \ \ \ cnt\ -\/=\ MPU\_TYPE\_RALIASES;}
\DoxyCodeLine{00268\ \ \ \}}
\DoxyCodeLine{00269\ \ \ ARM\_MPU\_OrderedMemcpy(\&(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaad8182e72fe5037a6ba1eb65a1554e0b}{MPU}}-\/>RBAR),\ \&(table-\/>\mbox{\hyperlink{struct_a_r_m___m_p_u___region__t_afe7a7721aa08988d915670efa432cdd2}{RBAR}}),\ cnt*rowWordSize);}
\DoxyCodeLine{00270\ \}}
\DoxyCodeLine{00271\ }
\DoxyCodeLine{00272\ \textcolor{preprocessor}{\#endif}}

\end{DoxyCode}
